A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms

We have developed a power performance tradeoff methodology for portable reconfigurable computing systems. There are two basic techniques which we employ to vary the power and performance of the application: frequency change and core change. For this methodology we implement a given algorithm with varying power performance levels: we call these implementations, Cores. Each core is characterized in terms of its power and performance levels and this information is included as a header in each core. We identify three scenarios with different goals: maximization of total work done, battery life time extension and weighted combination of work done and battery lifetime. We divide the total energy available in the battery into fixed slots which we call reconfiguration slots. Integer Linear Program formulations are used to find the best constraint-satisfying sequence of cores offline. Each chosen core in the sequence is allowed to execute until its energy quantum is exhausted. We tested this methodology with three example designs: FFT, DCT and a Parallel Multiplier.